This invention relates to a semiconductor memory, more particularly to the circuits for generating transfer gate signals in a semiconductor memory with shared sense amplifiers.
To conserve power and obtain an adequate operating margin, the memory cells in a semiconductor memory are commonly divided into a plurality of arrays, only one of which is activated in any given access cycle. This leads to a configuration in which sense amplifier arrays are disposed between memory cell arrays, with each sense amplifier array shared by the memory cell arrays on either side. Transfer gate signals control interconnections between the memory cell arrays and sense amplifier arrays.
In the standby state, to precharge bit lines in the memory cell arrays, it suffices to drive the transfer gate signals to the supply voltage level. During an access cycle, however, the transfer gate signals associated with the accessed memory cell array must be driven to a higher level, to enable writing or refreshing of data at the full supply-voltage level.
Prior-art semiconductor memories of this type accordingly provide, for each transfer gate signal, a transfer gate driver having a charge pump for generating an elevated voltage. In densely integrated memories, in which each transfer gate signal must drive the gate capacitance of a large number of gate transistors, the charge pump requires a large capacitor, so the transfer gate drivers take up considerable space. Moreover, they must be located at some distance from the sense amplifier arrays, a requirement that lengthens the transfer gate signal lines and increases their resistance and capacitance.
Prior-art transfer gate drivers also rely on delay lines for timing control. These delay lines are a source of various problems, such as inefficient charge pumping or unwanted current flow from the power supply to ground. These problems occur when the timing is improperly adjusted, as a result of fabrication variations, for example.